Dielectric layer forming method and devices formed therewith

ABSTRACT

Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric layers. Such embodiments include forming metal-containing dielectric layers over a silicon-containing substrate where a metal-containing layer is first formed and that treated to form a dielectric layer. Dielectric layers formed by methods of the present invention have a dielectric constant greater than that of silicon dioxide, and can have an equivalent oxide thickness of less than 2 nanometers. Such dielectric layers are useful in the forming of a variety of semiconductor devices such as transistors, capacitors and the like where such devices and integrated circuits formed from such devices are encompassed by embodiments in accordance with the present invention.

TECHNICAL FIELD

[0001] The present invention relates generally to methods of formingdielectric layers and the devices fabricated therewith. Morespecifically, the present invention relates to methods of formingdielectric layers having high dielectric constants by depositingoxidizable materials over a semiconductor substrate and oxidizing thematerials to form amorphous oxides. The invention also pertains todevices formed employing such oxides.

BACKGROUND

[0002] Increasing the performance of integrated circuits (ICs), bothwith regard to more complex functionality and higher speeds, is aprimary goal of efforts in advancing the semiconductor arts. One methodthat has been extensively employed to achieve this goal is scaling, thatis decreasing area or size of individual device components that are usedto form such integrated circuits. For example, the gate length of atypical MOS transistor has been reduced over the past several years fromseveral microns to fractions of a micron and gate lengths of 0.1 micronor less will soon be desired. Such scaling efforts have also effectedthe size of capacitors used in a variety of ICs such as DRAMS and SRAMS(dynamic and static random access memories, respectively).

[0003] While such scaling efforts have resulted in the desired increasesin performance, generally such size reductions also impact at least somecharacteristics of the devices so “scaled.” For example, reducing thegate length of a transistor generally reduces the transistor's outputand decreasing the size of a capacitor generally reduces the capacitanceor amount of charge such a capacitor can store. Fortunately, changingother features of devices such as transistors and capacitors has made itpossible to retain or at least control such changes in theiraforementioned characteristics. Thus as transistor gate length has beenreduced, the gate dielectric layer's thickness has also been reduced toat least partially compensate for the change in device output.Similarly, as the size of capacitor structures has been reduced,materials such as hemispherically grained polysilicon (HSG) have beenemployed to increase the effective surface area of such structures andcompensate, at least in part, for such size reductions.

[0004] However, it appears likely that as scaling continues suchexemplary compensation techniques may not be possible. Silicon dioxide(SiO₂), with a dielectric constant of about 3.9, remains the most commonmaterial employed for gate dielectric layers. To maintain transistoroutput at an acceptable level, a transistor having a gate length of 0.1micron will require an ultra-thin SiO₂ layer with a thickness of about 2nanometers (nm). Ultra-thin being defined herein as a thickness of about5 nm or less.

[0005] The forming and use of such ultra-thin SiO₂ layers is problematicfor a variety of reasons since such layers consist of only a few layersof molecules. Thus only one additional or missing layer of molecules canhave a dramatic effect on device performance; for example where adesired layer is four SiO₂ molecules thick, a change of one moleculewill change a characteristic such as the layer's capacitance by as muchas 25%. In addition, such thin layers typically exhibit high currentleakage, for example due to band to band or Fowler-Nordheim tunneling.Such layers are also more susceptible to dopant penetration or diffusionthrough the layer thus changing the characteristics of an adjacent layeror region; for example boron diffusion from the gate electrode into thechannel region alters channel characteristics.

[0006] One method of reducing these problems is the use of a thickerlayer of an alternative dielectric material such as a metal oxide havinga higher dielectric constant than that of SiO₂. For the purpose ofillustration, a metal oxide gate dielectric having an appropriately highdielectric constant can be formed with a thickness several times that ofa SiO₂ layer while having the performance characteristics of the thinnerSiO₂ layer. Thus the thicker metal oxide layer is said to have theequivalent oxide thickness (EOT) of the thinner layer. Alternate metaloxide materials such as titanium oxide (TiO₂), aluminum oxide (Al₂O₃),tantalum oxide (Ta₂O₅) and others have therefore received attention asreplacements for SiO₂. However, such alternate materials must exhibit,in addition to a high dielectric constant (greater than that of SiO₂), alarge band-gap with a favorable band alignment, low interface statedensity, good thermal stability and the ability to be formed in a mannerconsistent with known semiconductor process methods at reasonable costand yield. Unfortunately, many candidate metal oxide materials having anappropriately high dielectric constant, cannot meet these additionalrequirements. Thus it would desirable provide alternate dielectricmaterials and methods of forming such materials that are appropriate asa replacement for ultra-thin SiO₂ layers.

SUMMARY

[0007] Embodiments in accordance with the present invention providedielectric materials, methods of forming such dielectric materials, andsemiconductor devices that employ such dielectric materials. Suchembodiments provide for the forming of a first metal-containingdielectric layer over a silicon-containing surface of a substrate andthe forming of a second metal-containing dielectric layer on the firstlayer. In embodiments of the present invention, the first and secondmetal-containing dielectric layers encompass elements selected fromGroup IVB and Group IIIB of the Periodic Table of Elements,respectively.

[0008] In some embodiments, a silicon dioxide layer is first formed anda first metal-containing layer is formed overlying such silicon dioxidelayer. Advantageously, the metal of the first layer encompasses anelement that can combine with the oxygen of the silicon dioxide to forma metal oxide material of the first metal-containing dielectric layerand chemically reduce the silicon dioxide to silicon.

[0009] In some embodiments in accordance with the present invention, oneor more metal-containing layers are exposed to an atmosphere thatencompasses oxygen while heating the exposed layers to a temperatureeffective to transform such metal-containing layers to metal-containingdielectric oxide layers. In some embodiments, such exposing encompassesion bombardment of the metal-containing layers, and in some embodimentssuch exposing encompasses providing oxygen radicals to themetal-containing layers.

[0010] Embodiments in accordance with the present invention provide forforming the first and second metal-containing dielectric layers having awide ratio of relative thicknesses, for example from a ratio of about1:5 to about 5:1 or greater. In embodiments of the present invention,such forming can be provided by physical vapor deposition (PVD) where ametal-containing layer of each formed layer is first deposited having athickness of about 10 nanometers (nm) or less. In embodiments of thepresent invention, such PVD methods include electron beam evaporationtechniques or other methods for forming high purity material layers byPVD. For example in some embodiments, radio frequency or microwaveenergy is employed for heating rather than an electron beam.

[0011] Embodiments of the present invention can encompass semiconductordevices such as MOS transistors, capacitors and the like. Such devicesare formed using metal-containing dielectric layers in accordance withthe present invention.

[0012] Some embodiments encompass integrated circuits such as dynamicand static random access memories (DRAMs and SRAMs) which includetransistors, capacitors and the like that are formed employingmetal-containing dielectric layers in accordance with the presentinvention, where such layers are also formed by methods in accordancewith the present invention. In some embodiments of the presentinvention, semiconductor devices encompassing a metal-containingcontaining dielectric layer have an equivalent oxide thickness (EOT) of2 nm to 5 nm. Advantageously, metal-containing dielectric layers inaccordance with the present invention having an EOT of less than 2 nmare also possible.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Embodiments in accordance with the present invention aredescribed below with reference to the following accompanying drawings.

[0014]FIG. 1 is a cross-sectional view of a semiconductor wafer fragmentdepicting an embodiment in accordance with the present invention at anearly step in the formation of a dielectric layer.

[0015]FIG. 2 is a cross-sectional view of a semiconductor wafer fragmentdepicting the embodiment of FIG. 1 at a subsequent step in the formationof a dielectric layer.

[0016]FIG. 3 is a cross-sectional view of a simplified representation ofan MOS transistor formed in accordance with embodiments of the presentinvention.

[0017]FIG. 4 is a cross-sectional view of a simplified representation ofa capacitor structure formed in accordance with embodiments of thepresent invention.

DETAILED DESCRIPTION

[0018] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0019] Embodiments in accordance with the present invention will bedescribed with reference to the aforementioned figures. Variousmodifications, adaptations or variations of the specific methods and orstructures described may become apparent to those skilled in the art asembodiments of the present invention are described. All suchmodifications, adaptations or variations, that rely upon the teachingsof the present invention, and through which these teachings haveadvanced the art, are considered to be within the scope and spirit ofthe present invention.

[0020] To aid in interpretation of the description of the illustrationsand claims that follow, the term “semiconductor substrate” is defined tomean any construction encompassing silicon semiconductive material,including, but not limited to, bulk silicon semiconductive materialssuch as a silicon semiconductor wafer (either alone or in assembliesencompassing other materials thereon) and silicon semiconductivematerial layers (either alone or in assemblies encompassing othermaterials). The term “substrate” refers to any supporting structure,including, but not limited to, the semiconductor substrates describedabove. In addition, the terms “high dielectric constant material” or“hi-K material” are used interchangeably herein and refer to materialshaving a dielectric constant that is greater than that of thermallygrown silicon dioxide, which is generally understood to have a value ofapproximately 3.9 or higher.

[0021] Referring to FIG. 1, semiconductor wafer fragment 10 a is showndepicted at an early processing step of an embodiment in accordance withthe present invention. Wafer fragment 10 a encompasses a semiconductivesubstrate 20, shown having a surface 22, a silicon dioxide layer 30overlying surface 22, a first metal-containing layer 40 overlying layer30 and a second metal-containing layer 50 overlying layer 40.

[0022] As described above, semiconductive substrate 20 is defined tomean any construction encompassing silicon semiconductive material.Generally a cross-sectional representation of such a semiconductivesubstrate 20, will include a variety of doped regions as are needed toform semiconductor device structures. Some of such doped regions, forexample well regions, being present even at an early stage ofprocessing. However, for ease of understanding the present invention,such doped regions that may be present are not shown in FIG. 1.

[0023] Surface 22 is an outermost boundary of substrate 20. Forillustrative purposes, surface 22 can be an upper surface of a singlecrystal silicon substrate, an epitaxially grown silicon layer or anyother appropriate silicon-containing material. Silicon dioxide layer 30is an optional layer. That is to say that, in some embodiments of thepresent invention such a layer is present at this early stage in theprocessing and in some it is not present. In addition, it will beunderstood that in those embodiments where the optional silicon dioxidelayer 30 is present, such layer is either a “native” oxide layer or anoxide layer that is formed to have a specific thickness by a processselected for the forming of such a layer. Where silicon dioxide layer 30is a “native” oxide layer, it will be understood that such a layer isformed spontaneously upon exposure of silicon surface 22 to anoxygen-containing ambient, generally at or near room temperature.Alternatively, where silicon dioxide layer 30 is a purposely grownlayer, such layer results from exposure of surface 22 to oxidizingconditions such as an oxidizing ambient, at an elevated temperature.Furthermore it will be understood that “native” oxide layers areessentially self-limiting in thickness and are generally limited toabout one or two molecular mono-layers in thickness. However, wherelayer 30 is a purposely grown layer, such layer can be formed havingessentially any thickness and where employed in embodiments of thepresent invention, is typically grown to a few nanometers in thickness,for example, 5 nanometers or less, although any other thickness is alsoappropriate.

[0024] Generally, where electrical contact to surface 22 is desired, itis known to remove such a layer as oxide layer 30 from over all or someportions of surface 22 prior to forming any layer from which theelectrical contact will be made. For example, Maiti et al. (U.S. Pat.No. 6,020,024, entitled “Method for Forming High Dielectric ConstantMetal Oxides,” hereinafter US'024) state at column 2, lines 61-65, thatsemiconductor substrate 12 (FIG. 1) “has preferably been pre-cleaned inorder to minimize the oxide at its surface with an HF clean and/orhydrogen (H₂) anneal step. In an alternative, a plasma N₂O process maybe used to remove substrate native oxide.” As will be described below,embodiments in accordance with the present invention can advantageouslyeliminate such a processing step. That is to say, that in someembodiments of the present invention, where a silicon oxide layer 30 isformed or allowed to form, no specific removal step is needed.

[0025] Still referring to FIG. 1, first metal-containing layer 40 isshown overlying optional silicon oxide layer 30. Layer 40 is generallyformed of a metal selected from the elements of Group IVB of thePeriodic Table of the Elements. As known, such group is generallyunderstood to include the elements titanium (Ti), zirconium (Zr),hafnium (Hf) and rutherfordium (Rf) which generally form chemically andthermally stable oxides having attractively high dielectric constants,for example the oxide of hafnium is reported to have a dielectricconstant (k) of about 27. While embodiments of the present inventionencompass any of the Group IVB elements, it has been found that ahafnium-containing layer 40 is advantageous since (1) hafnium oxide(HfO₂) is the most stable oxide of the group of oxides, (2) hafnium iscapable of reducing a silicon oxide layer, (3) hafnium suicide isreadily oxidized and (4) HfO₂ is resistive to impurity diffusion.

[0026] In some embodiments of the present invention, the thickness oflayer 40 will be 1 nanometer (nm) or less, while in other embodimentsthe thickness will be as much as approximately 5 nm or more. Suchvariations in thickness are a function of, among other things, the useor non-use of the optional silicon dioxide layer 30, and the purpose forwhich a finally formed dielectric layer, in accordance with the presentinvention, is intended. For example, as will be discussed below, in someembodiments of the present invention a gate dielectric layer is formedand in other embodiments of the present invention a capacitor dielectriclayer is formed. As one of ordinary skill in the art is aware, thethickness of such layers can vary widely.

[0027] Metal-containing layer 40 is most advantageously formed by aphysical vapor deposition process (PVD). While any of the several commonPVD processes such as sputtering or evaporation can be used, it is foundadvantageous to use an evaporative processes and in particular anelectron beam evaporative process. For example, where an electron beamevaporative process is employed, it is found that an initial puritylevel of the source material for the PVD process can be provided tolayer 40. That is to say that the level of purity of the source materialand initially deposited metal-containing layer is essentially unchanged.However, it will be understood that the other methods of formingmetal-containing layer 40 are within the scope and spirit of the presentinvention, for example evaporation methods where a heating source otherthan an electron beam is employed or any other appropriate PVD methodcapable of providing the initial purity level of the source material tolayer 40, can also be advantageously used.

[0028] Still referring to FIG. 1, second metal-containing layer 50 isshown overlying first metal layer 40. In accordance with embodiments ofthe present invention, metal-containing layer 50 is advantageouslyformed of a metal selected from the elements of Group IIIB of thePeriodic Table of the Elements. As known, Group IIIB is generallyunderstood to encompass scandium (Sc), yttrium (Y), lanthanum (La) andactinium (Ac). Embodiments of the present invention encompass Group IIIBelements, as such elements form dielectric oxides that have highthermodynamic stability and a generally suitable dielectric constant. Ofsuch Group IIIB elements, it has been found that a lanthanum-containinglayer 50 is advantageous at least because (1) lanthanum oxide (La₂O₃)has a dielectric constant similar to that of HfO₂ (k=27 for La₂O₃ andk=24 for HfO₂) and (2) La₂O₃ has high thermodynamic stability. Thuschanges in the relative thickness for layers 40 and 50 that can changethe ratio of thicknesses for the layers from between about 1:5 to about5:1, will result in only small changes, if any, in the dielectricconstant of the stacked oxide layer subsequently formed.

[0029] Generally, metal-containing layer 50 is formed in the same manneras is metal-containing layer 40. That is to say, by using a physicaldeposition (PVD) method as previously described. However, while layers40 and 50 can be formed in distinct PVD processes, it is generallyadvantageous to form both layers using a single, unified PVD process.For example, such a unified deposition or forming process wouldgenerally provide that substrate 10 a is placed into a PVD system and amaterial of the first metal-containing layer 40 is formed thereon untila desired thickness of layer 40 is formed. In some embodiments, once afirst thickness of first layer 40 is obtained, the forming of firstlayer 40 is stopped and a forming of second layer 50 is begun within thesame PVD system. Subsequently, the forming of second layer 50 is stoppedonce a desired second thickness for such layer is obtained or when adesired total thickness of layers 40 and 50 is obtained.

[0030] In some embodiments, after the first thickness of layer 40 isformed, the forming of layer 50 is begun without a prior stopping of thedeposition of the material of layer 40. In this manner the material ofsecond metal-containing layer 50 will be combined with some material offirst metal-containing layer 40 in at least an interfacial region (notshown) of such second layer 50. It will be understood that in someembodiments, such a mixing of the materials of first layer 40 and secondlayer 50 is limited to such an interfacial region by stopping theforming of the material of layer 40 after the forming of the material oflayer 50 is started. In other embodiments, the forming of the materialof layer 40 is not stopped once the forming of the material of layer 50is started, rather both materials are formed until a desired thicknessis obtained thus, essentially all of second layer 50 is a mixture ofmaterials. In addition, as discussed for first metal-containing layer40, a desired thickness for second metal-containing layer 50 can alsovary as a function of the several factors mentioned for layer 40 as wellas the thickness of first layer 40 previously deposited. Thus, thethickness of such layer 50 generally has the same range as providedabove for the thickness of layer 40.

[0031] It has also been found that in some embodiments in accordancewith the present invention a specific ratio of thickness for first layer40 to second layer 50 is advantageous. For example where an optionalsilicon oxide layer 30 is used, generally a thin layer of ahafnium-containing metal layer 40 is formed, about 1 nm or less, andemployed to reduce such silicon oxide layer 30 prior to forming secondlayer 50. The subsequent second metal-containing layer 50 is formed withan appropriate thickness, for example a layer of lanthanum-containingmetal having a thickness of between about 3 to 5 nm. Advantageousthickness ratios of first metal-containing layer 40 to secondmetal-containing layer 50 have been found to vary with ratios from about1:5 to about 5:1 being typical.

[0032] Turning now to FIG. 2, a cross-sectional view of a semiconductorwafer fragment 10 b depicting the embodiment of FIG. 1 at a subsequentprocessing step is depicted. As shown, a first metal-containingdielectric layer 45 overlies surface 22 of semiconductive substrate 20and a second metal-containing dielectric layer 55 overlies the firstlayer 45.

[0033] First metal-containing dielectric layer 45 and secondmetal-containing dielectric layer 55 are formed from firstmetal-containing layer 40 and second metal-containing layer 50 (of FIG.1), respectively. Generally, a transformation from metal-containinglayers to metal-containing dielectric layers is performed. Suchtransformation typically encompassing oxidizing the metal-containinglayers to form amorphous metal oxide containing material layers. In someembodiments of the present invention, such an oxidation process isaccomplished after deposition of both the first and secondmetal-containing layers. In other embodiments oxidation of the firstmetal-containing layer to form the first metal-containing dielectriclayer precedes formation of the second metal-containing layer. In yetother embodiments of the present invention, oxidation of one or both ofthe metal-containing layers is performed, during the forming of one orthe other of such layers. By means of example, in one such method whereoptional silicon oxide layer 30 is present, a hafnium-containing layer40 is formed over layer 30 and subsequently exposed to conditions suchthat the hafnium of layer 40 combines with the oxygen of silicon oxidelayer 30 to form a hafnium-containing dielectric layer 45 comprisinghafnium oxide (HfO₂). Such a method of forming a metal oxide by thechemical reduction of silicon dioxide of layer 30 to silicon makes itpossible to skip the separate removal step for the silicon oxide layerthat is taught by Maiti et al. in the previously mentioned US'024. Itwill be noted that since silicon dioxide layer 30 is reduced to silicon,the thickness of such layer 30 is combined with substrate 20 in FIG. 2.When such hafnium metal-containing layer is oxidized, a secondlanthanum-containing layer is formed and subsequently oxidized by anappropriate method. While such example specifically refers to Hf and La,it will be understood that the other elements of Group IVB and IIIB,such as Zr and Y, respectively, could also be employed, although therelative reactivity of the materials will vary.

[0034] Generally, conditions for the chemical reduction of optionalsilicon oxide layer 30 with the material of layer 40 encompass providingtemperatures between about 200° C. and 400° C. as an inert atmosphere istypically provided such that layer 30 is essentially the only source ofoxygen present. However, where silicon oxide layer 30 is not present, orafter the chemical reduction of such silicon dioxide layer, othermethods for the oxidation of portions of layer 40 not completelyoxidized and/or layer 50 are employed. Such other methods include, butare not limited to, the use of remotely formed oxygen radicals; ionbombardment of such metal layers with oxygen ions and thermal oxidationof such layers in an oxygen comprising atmosphere at appropriatetemperatures. Typically such low energy ion bombardment is performedusing relatively high plasma densities, typically above 10¹²/cm³, andlow electron temperature, generally less than 1.3 eV, and where oxygenradicals are used, generally such radicals are formed using appropriateradio frequency or microwave energy which is applied to an oxygencomprising gas stream at a reduced pressure. In addition, generally theuse of ion bombardment and/or oxygen radicals is provided in combinationwith a thermal treatment. By means of example, it is found effective toconvert metal-containing layers 40 and 50 to their respectivemetal-containing dielectric layers 45 and 55 by providing ionbombardment of the layers using a mixed gas with about 3% to 5% oxygenin an inert carrier such as Ar or Kr. The layers are held in such gasmixture at a pressure of about 1 Torr and a temperature of about 250° C.to about 300° C. with a microwave power source applying a power densityof about 3-7 W/cm². It will be understood that such oxidation conditionsonly one effective method and that other appropriate and effectivemethods can be used to form one or both of dielectric layers 45 and 55from layers 40 and 50 either collectively or individually.

[0035] Referring to FIG. 3, an MOS transistor 14 formed in accordancewith embodiments of the present invention is depicted. Gate dielectric60 is disposed over a portion of surface 22 of substrate 20 as well asadjacent to and elevationally above source/drain (S/D) regions 24. Inaccordance with embodiments of the present invention, gate dielectric 60encompasses metal-containing dielectric layers 45 and 55 (FIG. 2) wheresuch layers are formed as described above and subsequently patternedusing any of the appropriate methods for patterning a gate electrode anddielectric. S/D regions 24 and sidewall spacers 70 are also formed byappropriate methods. It will be understood that transistor 14 is asimplified transistor representation, and that more complex transistorstructures are also encompassed by embodiments of the present invention.For example, in some embodiments, transistor 14 is a MOSFET having angate dielectric layer 60 that has an equivalent oxide thickness (EOT) of2 nm or less while having an actual thickness of as much as about 6 nm.Such an advanced MOSFET can also have a gate length of about 0.25 micronor less and be encompassed within an integrated circuit such as adynamic random access memory (DRAM), static random access memory (SRAM)or any of the various other memory integrated circuits. Transistor 14can also encompass a gate dielectric layer 60 that has an EOT of greaterthan 2 nm and a gate length of more than 0.25 micron.

[0036] Transistor or integrated circuit embodiments in accordance withthe present invention that have an equivalent oxide thickness of about 2nm or less, advantageously provide for readily forming gate dielectriclayer 60 having a desired EOT that would not be otherwise practical.Thus, methods for incorporating materials with high-dielectricconstants, such as oxides of Group IIIB and IVB metals, over a siliconsubstrate are provided where such materials can be formed into a stackedamorphous metal oxide-containing gate dielectric structure such as gatedielectric 60.

[0037] Turning now to FIG. 4 a simplified capacitor structure 16, formedin accordance with embodiments of the present invention, is depicted.Capacitor structure 16 is shown overlying a doped region 26, disposed insemiconductive substrate 20. A lower capacitor electrode 82 electricallycontacts region 26, a capacitor dielectric 64 overlies electrode 82 anda second capacitor electrode 86 overlies capacitor dielectric 64.

[0038] Capacitor dielectric 64 is advantageously formed from first andsecond metal-containing layers deposited over lower electrode 82 in amanner analogous to that described previously with FIGS. 1 and 2. Thus,after first forming and patterning lower capacitor electrode 82, firstand second metal-containing layers (not shown) are formed andtransformed by appropriate methods into metal-containing dielectriclayers which are encompassed within capacitor dielectric layer 64.

[0039] The previously described methods of converting Group IVB and IIIBmetals into metal oxides are not limited to extremely thin films, thusthicker metal-containing layers, suitable for forming capacitordielectric layers having a thickness of 10 nm or more, can be firstdeposited and then transformed into a metal-containing dielectric layer.As previously mentioned, Group IVB metal oxides in general and HfO₂ inparticular, are/is resistant to impurity diffusion so that suchmaterials can be oxidized over a lower capacitor electrode 82 formedfrom silicon-comprising materials such as any of the various forms ofpolycrystalline silicon without oxidizing such lower electrode 82.

[0040] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. In addition, advantages of the invention of the instantapplication have become apparent by and through the descriptions andexamples provided. Thus it will be understood that the use of stackedamorphous gate oxide layers formed of Group IVB and IIIB metal oxidesadvantageously provides a final layer that has a high dielectricconstant of about 27 to 29, and is both thermally stable and protectiveof underlying layers to impurity diffusion. It will be understood thatthe selection of Hf and La form the metal-containing layers isparticularly advantageous although other metals from Group IVB and IIIBare also appropriate. It is to be understood, however, that theinvention is not limited to the specific features shown and described,since the means herein disclosed comprise preferred forms of putting theinvention into effect. The invention is, therefore, claimed in any ofits forms or modifications within the proper scope of the appendedclaims appropriately interpreted in accordance with the doctrine ofequivalents.

We claim:
 1. A method of forming a dielectric layer comprising:providing a substrate comprising a silicon-containing surface; forming afirst metal-containing dielectric layer over the surface, the metalcomprising an element selected from Group IVB of the periodic table; andforming a second metal-containing dielectric layer over the firstmetal-containing dielectric layer.
 2. The method of claim 1, wherein thefirst metal-containing dielectric layer comprises hafnium.
 3. The methodof claim 1, further comprising: forming a layer of silicon dioxideoverlying at least one portion of the surface; and wherein forming thefirst metal-containing dielectric layer comprises; forming a metal layerover the layer of silicon dioxide; and combining metal of the metallayer with oxygen of the silicon dioxide layer to form a metal oxidedielectric material.
 4. The method of claim 3, wherein the metal layercomprises hafnium.
 5. The method of claim 4, wherein the combiningcomprises providing conditions effective for the hafnium of the metallayer to chemically reduce the silicon dioxide layer.
 6. The method ofclaim 1, where the second metal-containing dielectric layer comprises anelement selected from Group IIIB of the periodic table.
 7. The method ofclaim 1, where the second metal-containing dielectric layer compriseslanthanum.
 8. The method of claim 1, where the forming of the firstmetal-containing dielectric layer and the second metal-containingdielectric layer comprise: forming a hafnium-containing layer; forming alanthanum-containing layer over the hafnium-containing layer; andexposing the hafnium-containing layer and the lanthanum-containing layerto an oxygen comprising atmosphere and heating the hafnium-containinglayer and the lanthanum-containing layer to a temperature effective toform a hafnium-containing dielectric layer and a lanthanum-containingdielectric layer.
 9. The method of claim 8, where forming thehafnium-containing layer and the lanthanum-containing layer comprisesphysical vapor deposition.
 10. The method of claim 8, where the exposingcomprises ion bombardment of the first hafnium-containing layer and thelanthanum-containing layer using an ion bombardment energy of about 10electron volts (eV) or less.
 11. The method of claim 10 where theheating comprises heating to a temperature from about 200° C. to about400° C. during the ion bombardment.
 12. The method of claim 8, where theexposing comprises positioning the substrate within a reaction chamberand exposing the hafnium-containing layer and the lanthanum-containinglayer to oxygen radicals within the reaction chamber.
 13. The method ofclaim 8, where: the forming the hafnium-containing dielectric layercomprises depositing hafnium to a thickness less than or equal to about5 nanometer (nm); and the forming the lanthanum-containing dielectriclayer comprises depositing lanthanum to a thickness less than or equalto about 5 nm.
 14. The method of claim 13 comprising a ratio of thehafnium thickness to the lanthanum thickness of from about 1 to 3 toabout 1 to
 4. 15. The method of claim 8, where; the forming thehafnium-containing dielectric layer comprises forming a layer containinghafnium to a thickness of about 1 nm; the forming thelanthanum-containing dielectric layer comprises forming a layercontaining lanthanum to a thickness no greater than about 5 nm; andwherein a ratio of thicknesses of the hafnium-containing layer to thelanthanum-containing layer is from about 1 to 3 to about 1 to
 4. 16. Themethod of claim 1, where the forming of the first and secondmetal-containing dielectric layers comprises physical vapor deposition.17. The method of claim 16, where physical vapor deposition compriseselectron beam evaporation.
 18. The method of claim 1, where forming thefirst metal-containing dielectric layer and the second metal-containingdielectric layer comprises forming the layers to have respectivethicknesses having a ratio of from about 4:1 to about 1:4.
 19. Themethod of claim 1, where the first metal-containing dielectric layerconsists of hafnium oxide and the second metal-containing dielectriclayer consists of lanthanum oxide.
 20. A method for forming an MOStransistor, comprising: providing a semiconductor substrate having asurface comprising silicon; forming a hafnium-containing dielectriclayer overlying the surface; forming a lanthanum-containing dielectriclayer overlying the hafnium-containing dielectric layer; and forming agate electrode over the hafnium-containing and lanthanum-containingdielectric layers.
 21. The method of claim 20, where: the forming of thehafnium-containing dielectric layer dielectric layer comprises firstforming a hafnium-containing layer; the forming of thelanthanum-containing dielectric layer comprises second forming alanthanum-containing layer; and wherein the first forming and the secondforming encompass physical vapor deposition.
 22. The method of claim 21,where physical vapor deposition comprises electron beam evaporation. 23.The method of claim 20, further comprising forming a layer of silicondioxide over at least a portion of the surface comprising silicon, priorto the forming of the hafnium-containing dielectric layer.
 24. Themethod of claim 20, where the forming of the hafnium-containingdielectric layer and the lanthanum-containing dielectric layercomprises: first forming a hafnium-containing layer and second forming alanthanum-containing layer-over the substrate; and exposing the hafniumand lanthanum containing layers to an oxygen comprising atmosphere whileheating the hafnium and lanthanum layers to a temperature effective toform a hafnium-containing dielectric layer and a lanthanum-containingdielectric layer.
 25. The method of claim 24, where forming thehafnium-containing dielectric layer and the lanthanum-containingdielectric layer comprise forming oxides of hafnium and lanthanum,respectively.
 26. The method of claim 24, where the heating comprisesheating the hafnium and lanthanum containing layers to a temperaturefrom about 200° C. and 400° C.
 27. The method of claim 25, where: thehafnium-containing layer is formed over a layer of silicon dioxide; andfurther comprising providing conditions effective for thehafnium-containing layer to chemically reduce the layer of silicondioxide.
 28. The method of claim 25, further comprising: providing ionbombardment of the hafnium-containing layer and the lanthanum-containinglayer using an ion bombardment energy of about 10 eV or less and wherethe heating to an effective temperature comprises heating whileproviding ion bombardment to a temperature from about 200° C. to about400° C.
 29. The method of claim 25, where: the forming of thehafnium-containing layer comprises forming such layer having a thicknessno greater than about 5 nanometers; the forming of thelanthanum-containing layer comprises forming such layer having athickness no greater than about 5 nanometers; and wherein a ratio and asum of the thicknesses of the hafnium-containing layer to thelanthanum-containing layer is from about 1 to 4 to about 4 to 1 and nogreater than about 6 nm, respectively.
 30. The method of claim 29 wherethe thickness of the hafnium-containing layer is no greater than about 1nm.
 31. The method of claim 29 where the hafnium-containing dielectriclayer and the lanthanum-containing layer are collectively a gatedielectric layer, where the gate dielectric layer is formed having anequivalent oxide thickness less than or equal to 2 nm.
 32. A method offorming a capacitor structure, comprising: providing a first capacitorelectrode; forming a hafnium-containing dielectric layer overlying thefirst capacitor electrode; forming a lanthanum-containing dielectriclayer over the hafnium-containing dielectric layer; and forming a secondcapacitor electrode overlying the hafnium-containing andlanthanum-containing dielectric layers.
 33. The method of claim 32,where: the forming of the hafnium-containing dielectric layer comprisesforming a hafnium-containing metal layer having a first thickness; theforming of the lanthanum-containing dielectric layer comprises forming alanthanum-containing metal layer having a second thickness; and whereina ratio of the first thickness to the second thickness is from about 1to 4 to about 4 to
 1. 34. The method of claim 33 where the firstthickness is no greater than about 1 nm and the ratio of thicknesses isfrom about 1 to 3 to about 1 to
 4. 35. The method of claim 33, furthercomprising, prior to forming the second capacitor electrode, providingan oxygen comprising atmosphere effective to essentially completelyoxidize the hafnium-containing and lanthanum-containing metal layers.36. The method of claim 35, where providing the oxygen comprisingatmosphere further comprises heating the hafnium-containing andlanthanum-containing metal layers to a temperature from about 200° C. toabout 400° C.
 37. The method of claim 33, where: the providing the firstcapacitor electrode comprising providing a silicon-containing firstcapacitor electrode; and prior to forming the hafnium-containing metallayer, forming a layer of silicon dioxide over at least a portion of thesilicon-containing first capacitor electrode.
 38. The method of claim37, where the hafnium-containing metal layer is formed overlying atleast a portion of the layer of silicon dioxide; and further comprisingproviding conditions effective for the hafnium of the hafnium-containingmetal layer to chemically reduce at least a portion of the silicondioxide underlying such layer.
 39. An MOS transistor comprising: asemiconductor substrate having a silicon-containing surface; a gatedielectric layer comprising: a first metal-containing dielectric layercontacting the silicon-containing surface, the metal of themetal-containing layer being selected from Group IVB of the PeriodicTable of the Elements; a second metal-containing dielectric layercontacting the first-metal-containing dielectric layer; and a gateelectrode overlying the gate dielectric layer.
 40. The transistor ofclaim 39, where the gate dielectric layer comprises an equivalent oxidethickness of less than or equal to 2 nm.
 41. The transistor of claim 40,where the second metal-containing dielectric layer is spaced from thesilicon-containing surface by the first metal-containing dielectriclayer.
 42. The transistor of claim 41, where the first metal-containingdielectric layer comprises hafnium and the second metal-containingdielectric layer comprises lanthanum and where the firstmetal-containing dielectric layer and the second metal-containingdielectric layer have a total thickness of about 6 nm or less.
 43. Thetransistor of claim 42, where the hafnium-containing dielectric layerhas a first thickness and the lanthanum-containing dielectric layer hasa second thickness, the second thickness being from about one fourth tofour times the first thickness.
 44. The transistor of claim 39, where:the first metal-containing dielectric layer is a hafnium-containingdielectric layer having a first thickness no greater than about 1 nm;the second metal-containing dielectric layer is a lanthanum-containingdielectric layer having a second thickness of no greater than about 5nm; wherein a ratio of the first thickness to the second thickness isfrom about 1 to 3 to about 1 to 4; and the gate dielectric layer has anequivalent oxide thickness of less than or equal to 2 nm.
 45. Ancapacitor structure comprising: a first capacitor electrode; a capacitordielectric layer comprising; a hafnium-containing dielectric layercontacting the first capacitor electrode; a metal-containing dielectriclayer contacting the hafnium-containing dielectric layer, the metal ofthe metal-containing dielectric layer selected from Group IIIB of thePeriodic Table of the Elements; and a second capacitor electrodeoverlying the metal-containing dielectric layer.
 46. The capacitorstructure of claim 45, where the metal-containing dielectric layer isspaced from the first capacitor electrode by the hafnium-containingdielectric layer.
 47. The capacitor structure of claim 45, where: thehafnium-containing dielectric layer has a first thickness; themetal-containing dielectric layer comprises a lanthanum-containingdielectric layer having a second thickness; and wherein a ratio of thefirst thickness to the second thickness is from about 1 to 4 to about 4to
 1. 48. The capacitor structure of claim 47, where the ratio is fromabout 1 to 3 to about 1 to
 4. 49. A memory integrated circuit comprisinga transistor and/or a capacitor formed employing a dielectric layerconsisting of hafnium oxide, lanthanum oxide and/or mixtures thereof.50. The memory integrated circuit of claim 50 comprising a DRAM or anSRAM integrated circuit and the dielectric layer is a gate dielectriclayer.
 51. The memory integrated circuit of claim 50, where the gatedielectric layer has an equivalent oxide thickness less than or equal to2 nm.